The present disclosure relates to a semiconductor structure and a method of fabricating the same. More particularly, the present disclosure relates to a semiconductor structure including at least one field effect transistor (FET) having a high k/metal gate stack located on a semiconductor substrate, wherein the at least one FET has a desired threshold voltage value, improved short channel control, improved inversion carrier mobility and reduced external resistance. The present disclosure also provides a method of forming such a semiconductor structure.
One trend in modern integrated circuit manufacture is to produce semiconductor devices, such as field effect transistors (FETs), which are as small as possible. In a typical FET, a source and a drain are formed in an active region of a semiconductor substrate by implanting n-type or p-type impurities in the semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer.
In order to continue scaling of semiconductor devices, high k/metal gate stacks have been employed to reduce the effective gate dielectric thickness and gate leakage. However, higher threshold voltage Vt (due to an undesirable metal gate work function) and higher capacitance are concerns for high performance complementary metal oxide semiconductor (CMOS) applications. The above concerns are especially prevalent in p-type FETs in which no stable band edge metal gate is presently available.